Application of Structurally Synthesized Binary Decision Diagrams for Timing Simulation of Digital Circuits

Meeting the timing requirements is an important constraint imposed on highly integrated circuits, and the verification of timing of a circuit before manufacturing is one of the critical tasks to be solved by CAD tools. In this paper, we present a novel technique to speed up gate-level timing simulation that is based on Structurally Synthesized Binary Decision Diagrams (SSBDD), which have already found application as an efficient mathematical model to represent digital circuits. The new approach uses path delays instead of gate delays for tree-like subcircuits (macros). Therefore timing waveforms are calculated not for all internal nodes of the gate-level circuit, but only for outputs of macros. The macros are represented by SSBDDs, which enable a fast computation of delays for macros. We show that the speed-up of timing simulation is directly proportional to the average size of macros in the circuit. The new approach to speed up the timing simulation is supported by encouraging experimental results.